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jsspace 发表于 2016-10-11 11:34  2 n# z! l- u$ | j( {" V
漏液不可以接受，不管是否灌胶。
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8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to; y) m, g7 X9 S/ J6 m& ?+ S4 D
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.) e7 c: ~, W# A: h4 p
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:4 q6 e' L) n( T5 S
a) Opening of the ground fuse,0 J2 \* U! W+ e% P
b) Charring of the cheesecloth or tissue paper,
! p. q" ^4 ]: M0 a7 e: j) M$ `c) Emission of flame or molten material from the unit,
m' j0 W0 \- h nd) Ignition or dripping of a compound from the unit,
6 B' n6 N: H- V W$ d2 n) O( qe) Exposure of live parts that pose a risk of electric shock under the requirements for
% d5 c7 X9 b/ j- i" faccessibility of 7.2, or
: C/ J4 ]4 T4 Lf) Breakdown during the subsequent dielectric voltage withstand test.% ` X# P! O5 g, _2 {: w, j
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)$ N9 t0 ?* _: L
through (f) occurs.
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0 K$ M7 k& M; H) u# n8.7.2 Component failure test
* W- q B1 K" y8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall
- |! i q5 Z/ u; bnot exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In4 J8 B( i* Q( O) S6 ~/ l
preparation for component failure tests, the equipment, circuit diagrams, and component specifications5 |! ], \6 m/ X3 ]7 \3 b+ Z
are examined to determine those fault conditions that might reasonably be expected to occur. Examples5 M" M, H' ]( a& C6 G
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open( `; k/ Z1 U' I5 Z& A2 B8 g. [
circuits of resistors and internal faults in integrated circuits.. n/ ? H5 f5 h4 \$ u6 ?3 x
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need
* _0 q' e6 a* {. Y$ K6 P" U, r3 enot be evaluated for component failure.2 ?8 k$ H7 F+ z5 D3 |
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock3 n- t! n% O9 w& ]4 d
need not be subject to this test.
( Q# e/ C$ W5 H/ @0 J8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each- w4 s+ |$ u/ ?5 F# E
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as1 q& ~& z c- |$ w# R; Q6 F
determined by no visual.+ y8 d$ V, H7 g! k- X: E
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1 [3 j' [3 l, A6 e5 _3 m再核对一下标准看有没有答案？1 X7 B! i) n0 `/ W1 G
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39
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