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jsspace 发表于 2016-10-11 11:34 
+ s# N v* B: J# Z/ e漏液不可以接受，不管是否灌胶。
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8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to0 `- p1 `4 L5 {8 B4 }: u# B
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.
' m- H0 o* T! y5 z ^8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:& w# P& H7 G# `9 G; {+ D
a) Opening of the ground fuse,7 ^ I6 i6 K$ g" r
b) Charring of the cheesecloth or tissue paper,
" k, }$ |9 p0 i( j' r' m/ p; rc) Emission of flame or molten material from the unit,
- i+ d* Y8 o, Vd) Ignition or dripping of a compound from the unit,
& w6 X# x/ v* [3 X6 j/ z" {e) Exposure of live parts that pose a risk of electric shock under the requirements for( {: n1 \+ C0 w, R8 m3 E) P
accessibility of 7.2, or0 |; k( s8 \& O9 \' `5 X; R1 M
f) Breakdown during the subsequent dielectric voltage withstand test.
2 b K3 F% f9 }! |, A7 G5 o kOpening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)6 s, i9 e9 i" w# \
through (f) occurs.# |& I: ]: J3 I' V$ ], z; S" l
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- C) n& \$ Q. _! M8 ^5 ^* Y; [6 h/ e8.7.2 Component failure test; ^' Q9 U, r1 ~
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall
: D8 x- A N7 G7 P5 W: Lnot exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In9 L' A8 S6 Z! q" C+ ?% B5 G
preparation for component failure tests, the equipment, circuit diagrams, and component specifications1 q+ K4 b9 S4 Q5 L* |% s" Y" p
are examined to determine those fault conditions that might reasonably be expected to occur. Examples4 D# [ }4 @2 x
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open
8 z- l" L, f8 r% ~+ F$ j: dcircuits of resistors and internal faults in integrated circuits.$ }( B. ]- y* m7 q9 x
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need
% Q! u$ j% Z8 T: _: A. enot be evaluated for component failure.
. Q3 V$ E: X& k1 a+ zException No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock
3 V5 ?4 B. n& \, A/ x& `need not be subject to this test.
! V4 i3 i2 l6 K+ Q4 X% T8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each" u0 f J$ ]' O# F' n, V
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as O6 k( m' W" h8 u' a+ l: W5 ?6 a) C, K
determined by no visual.
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再核对一下标准看有没有答案？
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39
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