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jsspace 发表于 2016-10-11 11:34
% o' u4 U6 x5 m8 {0 u2 s# ]0 j$ L漏液不可以接受,不管是否灌胶。
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7 Q; B8 R" Z/ y, h8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to
5 {+ q6 c( D2 B6 Lroom temperature and the dielectric voltage withstand test of 8.6 shall be repeated.
# J, p& C$ e2 q0 Y# l$ R4 x8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:: T/ Z$ U2 |( l" n+ i0 h. c
a) Opening of the ground fuse,
8 e/ j- r, L! k3 c/ I2 T6 yb) Charring of the cheesecloth or tissue paper,3 A8 ?0 ~! d+ G: p9 Q& r
c) Emission of flame or molten material from the unit,
4 b2 B+ U. j9 Dd) Ignition or dripping of a compound from the unit,
# }$ c; l& w+ Q( Y" ?8 m: ke) Exposure of live parts that pose a risk of electric shock under the requirements for
( @5 C5 H, r- ^: y; vaccessibility of 7.2, or( R7 u: Y& W/ }! E' X, Y, Q
f) Breakdown during the subsequent dielectric voltage withstand test.5 f7 L4 P" o& c9 L3 `/ n
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)' a% S; o. _* u. ^+ O# j) l' O
through (f) occurs.
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8.7.2 Component failure test5 ?. t) D' e# P1 {# h/ u
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall( I+ i. D, [8 @+ k
not exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In! M8 n# p" c g1 @+ e ~6 S# D& W
preparation for component failure tests, the equipment, circuit diagrams, and component specifications
6 h! h. V/ s/ c, `2 G( s xare examined to determine those fault conditions that might reasonably be expected to occur. Examples# N9 ?8 D. b/ O' i5 w- i
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open
. D4 j- N% U/ W9 O# Y( K9 T: vcircuits of resistors and internal faults in integrated circuits.5 E- |. ?# G+ U
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need
$ C( ^3 m+ c% @' ?& S9 V& \not be evaluated for component failure.4 d8 e+ L; E5 n% [, ~" e) N
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock
4 Q% o3 P% T* u* Gneed not be subject to this test.
8 r$ O( m9 {3 g, L4 O. q8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each
& U) f$ v8 n" O3 v( F( ztest shall continue until either the unit is no longer operable, or until conditions are obviously stable (as
) E E' e( f& [determined by no visual.; A9 s& E5 R1 p' S* H
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再核对一下标准看有没有答案?
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